Paper(90~94)

1994

  • S. M. Kang, B. K. Whitlock, J. J. Morikuni, and E. Conforti, “Simulation of Optical Interconnects in High-Performance Computing and Communications,” SPIE Mtg., Los Angeles, CA, January 1994.
  • S. M. Kang, B. K. Whitlock, J. J. Morikuni, and E. Conforti, “Simulation of Optical Interconnects in High-Performance Computing and Communication Systems,” Optoelectronic Interconnects II, SPIE Proc., Vol. 2153, paper 29, pp. 238-250, Los Angeles, CA, January 27, 1994.
  • C. Diaz, S. M. Kang, and C. Duvvury, “Electrical Overstress Thermal Failure Simulation for Integrated Circuits,” IEEE Trans. on Electron Devices, Vol. 41, no. 3, pp. 359-366, March 1994.
  • C. H. Diaz and S. M. Kang, “Circuit-Level Electro-thermal Simulation of Electrical Overstress Failures in Advanced MOS I/O Protection Devices,” IEEE Trans. on Comput.-Aided Des., Vol. 13, no. 4, pp. 482-493, April 1994.
  • J. Kim, S. M. Kang, and S. S. Sapatnekar, “High Performance CMOS Macromodule Layout Synthesis,” 1994 Int. Symp. on Circuits and Syst., London, England, May 1994.
  • E. P. Olson and S. M. Kang, “State Assignment for Low-Power FSM using Genetic Local Search,” 1994 Int. Symp. on Circuits and Syst., London, England, May 1994.
  • J. Kim and S. M. Kang, “A New Triple-Layer OTC Channel Router,” 1994 IEEE Custom Integrated Circuits Conf., San Diego, CA, May 1994, pp. 647-650.
  • D.-H. Cho and S. M. Kang, “A New Deep Submicron Compact Physical Model for Analog Circuits,” 1994 IEEE Custom Integrated Circuits Conf., San Diego, CA, May 1994, pp. 41-44.
  • C.-C. Teng, W. Sun, and S. M. Kang, “iRULE: Fast Hot-Carrier Reliability Diagnosis using Macro-Models,” 1994 IEEE Custom Integrated Circuits Conf., San Diego, CA, May 1994, pp. 421-424.
  • E. Olson and S. M. Kang, “State Assignment for Low-Power FSM Synthesis using Genetic Local Search,” 1994 IEEE Custom Integrated Circuits Conf., San Diego, CA, May 1994, pp. 140-143.
  • T. Karnik and S. M. Kang, “A Hierarchical Partitioning of VHDL Structures,” 1994 IEEE VHDL Int. User’s Forum, Oakland, CA, May 1994, pp. 36-45.
  • Y. Leblebici and S. M. Kang, “Simulation of Hot Carrier Induced MOS Circuit Degradation for VLSI Reliability Analysis,” IEEE Trans. on Rel., Vol. 43, no. 2, pp. 197-206, June 1994.
  • T. Karnik, S. Ramaswamy, S. M. Kang, and P. Banerjee, “Application of Algorithm Based Fault Tolerance to High-Level Synthesis of Signal Flow Graphs,” Int. Symp. on Optics, Imaging, and Instrumentation, San Diego, CA, July 1994, pp 760-776.
  • J. J. Morikuni and S. M. Kang, “Optoelectronic Simulation at the Device and Circuit Level,” IEEE LEOS Mtg., Lake Tahoe, NV, July 1994, pp. 8-9.
  • J. J. Morikuni, A. Dharchoudhury, Y. Leblebici, and S. M. Kang, “Improvements to the Standard Theory of Photoreceiver Noise,” IEEE J. of Lightwave Technol., Vol. 12, no. 7, pp. 1174-1184, July 1994.
  • T. Karnik, D. G. Saab, and S. M. Kang, “Hierarchical Mixed-Level Simulation of VHDL Descriptions,” 1994 ASIC Conf., Rochester, NY, September 1994, pp. 170-173.
  • H. Duan, J. W. Lockwood, and S. M. Kang, “FPGA Prototype Queueing Module for High Performance ATM Switching,” Proc. 1994 ASIC Conf., Rochester, NY, September 1994, pp. 429-432.
  • B. K. Whitlock, J. J. Morikuni, and S. M. Kang, “Optimizing Component Specifications in Optical Interconnects using Mixed-Level Simulation,” in IEEE LEOS Annual Mtg., Vol. 1, Boston, MA, October 31, 1994, pp. 43-44.
  • S. Ramaswamy, E. Rosenbaum, and S. M. Kang, “Circuit-Level Electrothermal Simulation Techniques for Designing Output Protection Devices,” IEEE Int. Integrated Rel. Wkshp., Lake Tahoe, NV, October 1994, pp. 79-82.
  • A. M. Hill and S. M. Kang, “Genetic Algorithms Based Design Optimization of VLSI Circuits,” 1994 Int. Conf. on Evolutionary Comput., Jerusalem, Israel, October 1994.
  • A. Dharchoudhury, S. M. Kang, K. H. Kim, and S. H. Lee, “Fast and Accurate Timing Simulation with Regionwise Quadratic Models of MOS I-V Characteristics,” 1994 Int. Conf. on Comput.-Aided Des., San Jose, CA, November 1994, pp. 190-194.
  • A. Dharchoudhury, S. M. Kang, H. Cha, and J. H. Patel, “Fast Timing Simulation of Transient Faults in Digital Circuits,” 1994 Int. Conf. on Comput.-Aided Des., San Jose, CA, pp. 719-722, November 1994.
  • S. S. Sapatnekar, P. M. Vaidya, and S. M. Kang, “Convexity-Based Algorithms for Design Centering,” IEEE Trans. on Comput.-Aided Des., Vol. 13, no. 12, pp. 1536-1549, December 1994.
  • S. M. Kang, J. W. Lockwood, and H. Duan, “A Scalable Optoelectronic Network for Workstations,” in Defining the Global Information Infrastructure, Vol. CR56, S. F. Lundstrom, Ed. SPIE Press, 1994.


1993

  • S. G. Bishop, I. Adesida, J. J. Coleman, T. A. DeTemple, M. Feng, K. Hess, N. Holonyak, Jr., S. M. Kang, G. E. Stillman, and J. T. Verdeyen, “The Engineering Research Center for Compound Semiconductor Microelectronics,” Proc. of the IEEE, Vol. 81, no. 1, pp. 132-151, January 1993.
  • M. Sriram, S. M. Kang, “Performance-Driven MCM Routing Using a Second-Order RLC Tree Delay Model,” IEEE Int. Conf. on Wafer Scale Integration, January 1993, pp. 262-267.
  • J. Morikuni, M. Tong, K. Nummila, J. Seo, A. Ketterson, S. M. Kang, and I. Adesida, “A Monolithic Integrated Optoelectronic Photoreceiver using an MSM Detector,” 1993 IEEE Int. Solid-State Circuits Conf., San Francisco, CA, February 1993, pp. 178-179.
  • J. W. Lockwood, C. Cheong, S. Ho, B. Cox, S. M. Kang, S. G. Bishop, and R. H. Campbell, “The iPOINT Testbed for Optoelectronic ATM Networking,” Conf. on Lasers and Electro-Optics (CLEO’93), Baltimore, MD, May 1993, pp. 370-371.
  • M. Sriram and S. M. Kang, “iPROMIS: An Interactive Performance-Driven Multilayer MCM Router,” 1993 IEEE Multichip Module Conf., Santa Cruz, CA, March 1993, pp. 170-173.
  • Y. eblebici, W. Sun, and S. M. Kang, “Parametric Macromodeling of Hot-Carrier Induced Dynamic Degradation in MOS VLSI Circuits,” IEEE Trans. on Electron Devices, Vol 40, no. 3, pp. 673-676, March 1993.
  • J. D. Cho, S. Raje, M. Sarrafzadeh, M. Sriram, and S. M. Kang, “Crosstalk-Minimum Layer Assignment,” Proc. ACM/SIGDA Physical Des. Wkshp., Lake Arrowhead, CA, April 1993.
  • S. Sapatnekar, P. M. Vaidya, and S. M. Kang, “Feasible Region Approximation Using Convex Polytopes,” Proc. 1993 IEEE Int. Symp. on Circuits and Syst., Chicago, IL, May 1993, pp. 1786-1789.
  • E. J. Brauer and S. M. Kang, “Functional Verification of ECL Circuits Including Voltage Regulators,” 1993 IEEE Int. Symp. on Circuits and Syst., Chicago, IL, May 1993, pp. 1710-1713.
  • D. H. Cho and S. M. Kang, “An Accurate AC Characteristic Table Look-up Model for VLSI Analog Circuit Simulation Applications,” 1993 IEEE Int. Symp. on Circuits and Syst., Chicago, IL, May 1993, pp. 1531-1534.
  • Y. Leblebici, and S. M. Kang, “Modeling and Simulation of Hot-Carrier Induced Device Degradation in MOS Circuits,” IEEE J. of Solid-States Circuits, Vol. 28, no. 5, pp. 585-595, May 1993.
  • W. Jansz, W. Sun, Y. Leblebici, and S. M. Kang, “Fast Hot-Carrier Reliability Diagnosis using Macro-Models, Proc. Int. Symp. on VLSI Technol. Syst. & Appl., Taipei, Taiwan, May 12-14, 1993, pp. 128-132.
  • B. Whitlock, E. Conforti, and S. M. Kang, “iFROST: illinois FibeR-optic and Optoelectronic Systems Tool Kit for Simulation of Optical Interconnect Systems,” 1993 Optical Fiber Commun. Conf., San Jose, CA, May 1993.
  • C. Diaz, S. M. Kang, and C. Duvvury, “Thermal Failure Simulation for Electrical Overstress in Semiconductor Devices,” Proc. Int. Symp. on Circuits and Syst., Chicago, IL, May 1993, pp. 1389-1392.
  • J. D. Cho, S. Raje, M. Sarrafzadeh, M. Sriram, and S. M. Kang, “Crosstalk-Minimum Layer Assignment,” 1993 Custom Integrated Circuits Conf., San Diego, CA, May 1993, pp. 29.7.1-29.7.4.
  • M. Sriram and S. M. Kang, “Fast Approximation of the Transient Response of Lossy Transmission Line Trees,” Proc. 1993 IEEE/ACM Des. Automat. Conf., Dallas, TX, June 1993, pp. 691-696.
  • A. A. Ketterson, J.-W. Seo, M. Tong, K. Nummila, J. J. Morikuni, K.-Y. Cheng, S. M. Kang, and I. Adesida, “A MODFET-Based Optoelectronic Integrated Circuit Receiver for Optical Interconnects,” IEEE Trans. on Electron Devices, Vol. 40, no. 8, pp. 1406-1416, August 1993.
  • Y. H. Shih, Y. Leblebici, and S. M. Kang, “ILLIADS: A Fast Timing and Reliability Simulator for Digital MOS Circuits,” IEEE Trans. on Comput.-Aided Des., Vol. 12, no. 9, pp. 1387-1402, September 1993.
  • C. H. Diaz, C. Duvvury, and S. M. Kang, “Studies of EOS Susceptibility in 0.6um nMOS ESD I/O Protection Structures,” Proc. 15th EOS/ESD Symp., Orlando, FL, September 1993, pp. 83-91.
  • C. H. Diaz and S. M. Kang, “Circuit-Level Electrothermal Simulation for EOS/ESD Analysis,” SRC Techcon’93, September 1993, pp. 271-273.
  • S. M. Kang and J. J. Morikuni, “Integrated Optoelectronics for High-Performance Computing and Communications,” OSA Ann. Mtg. Tech. Digest, October 1993.
  • S. M. Kang and M. Sriram, “Multichip Modules for VLSI Systems Integration,” Proc. Int. Conf. on VLSI and CAD, November 1993, pp. 1.1-1.6. S.
  • H. Ho, E. Conforti, and S. M. Kang, “Monolithic Optical Equalizer Array for Wavelength-Reusable and Topology-Reconfigurable WDM Local Area Networks,” 1993 IEEE/LEOS Ann. Mtg., November 1993, pp. 416-417.
  • S. Sapatnekar, P. M. Vaidya, and S. M. Kang, “Convexity-Based Algorithms for Design Centering,” Proc. 1993 IEEE Int. Conf. on Comput.-Aided Des., Santa Clara, CA, November 1993, pp. 206-209.
  • S. Sapatnekar, V. B. Rao, P. M. Vaidya, and S. M. Kang, “An Exact Solution to the Transistor Sizing Problem for CMOS Circuits using Convex Optimization,” IEEE Trans. on Comput.-Aided Des., Vol. 12, no. 11, pp. 1621-1634, November 1993.
  • C. H. Diaz, C. Duvvury, S. M. Kang, and L. Wagner, “Electrical Overstress Power Profiles: A Guideline to Qualify EOS Hardness of Semiconductor Devices,” J. of Electrostatics, Vol. 31, pp. 161-176, November 1993.
  • C. H. Diaz, C. Duvvury, and S. M. Kang, “Electrothermal Simulation of Electrical Overstress in Advanced nMOS ESD Protection Devices,” 1993 IEEE Electron Devices Mtg., December 1993, pp. 131-134.
  • E. C. Chang and S. M. Kang, “Transient Simulation of Lossy Transmission Lines Using Piecewise Recursive Convolution,” Proc. 1993 Int. Symp. on Nonlinear Theory and Its Appl., Waikiki, HI, December 5-9, 1993, pp. 329-334.


1992

  • S. M. Kang, “Microelectronic and Optoelectronic Integration for Reliable High-Performance Systems,” Proc. KSEA/KOSEF Symp., January 1992.
  • A. Ketterson, M. Tong, J.-W. Tong, K. Nummila, J. Morikuni, K. Y. Cheng, I. Adesida, and S. M. Kang, “A High-Performance A1GaAs/InGaAs/GaAs Pseudomorphic MODFET-Based Monolithic Optoelectronic Receiver,” IEEE Photonic Tech. Lett., 4, p. 73, 1992.
  • A. Ketterson, M. Tong, J.-W. Tong, K. Nummila, K. Y. Cheng, J. Morikuni, K. Y. Cheng, I. Adesida, and S. M. Kang, “Submicron Modulation-Doped Field-Effect-Transistor / Metal-Semiconductor-Based Optoelectronic Integrated Circuit Receiver Fabricated by Direct-Write Electron Beam Lithography,” J. of Vac. Sci. and Tech., B10, p. 2936, 1992.
  • A. Ketterson, M. Tong, J.-W. Seo, K. Nummila, J. Morikuni, K. Y. Cheng, I. Adesida, and S. M. Kang, “A Submicron Pseudomorphic MODFET-based OEIC Receiver,” IEEE Photonics Technol. Lett., Vol. 4, no. 1, pp. 73-76, January 1992.
  • A. Dharchoudhury and S. M. Kang, “Systematic Identification of Correlated Device Model Parameter Values for Worst-Case Circuit Performance Analysis, ” 1992 VLSI Des., Banglore, India, January 1992.
  • G. M. Tharakan and S. M. Kang, “A New Design of a Fast N-Bit Barrel Switch Network,” IEEE J. of Solid-State Circuits, Vol. 27, no. 2, pp. 217-221, February 1992.
  • Y. Leblebici and S. M. Kang, “Modeling of nMOS Transistors for Simulation of Hot-Carrier-Induced Device and Circuit Degradation,” IEEE Trans. on Comput.-Aided Des., Vol. 11, no. 2, pp. 235-246, February 1992.
  • S. M. Kang, “Computer-Aided Design of Optoelectronic Subsystems,” Packaging, Interconnects, Optoelectronics for the Des. of Parallel Comput. Wkshp., Schaumburg, IL, March 1992, pp. 19-29.
  • J. J. Morikuni, D. S. Gao, and S. M. Kang, “Modeling of Optical Logic Gates for Computer Simulation,” IEE Proc. J. Optoelectronics, Vol. 139, no. 2, pp. 105-116, April 1992.
  • J. J. Morikuni and S. M. Kang, “An Analysis of High-Frequency Amplifier Inductive Peaking,” 1992 Int. Symp. on Circuits and Syst., May 1992, pp. 2848-2851.
  • W. Sun, Y. Leblebici, and S. M. Kang, “Design-for-Reliability Rules for Hot-Carrier Resistant CMOS VLSI Circuits,” 1992 Int. Symp. on Circuits and Syst., May 1992, pp. 1254-1257.
  • Y. Leblebici and S. M. Kang, “One-Dimensional Transient Device Simulation using a Direct Method Circuit Simulator,” 1992 Int. Symp. on Circuits and Syst., May 1992, pp. 895-898.
  • W. Sun, Y. Leblebici, and S. M. Kang, “A Parametric Macro-Model Approach for Hot-Carrier Resistant CMOS VLSI Design,” 1992 Custom Integrated Circuits Conf., May 1992, pp. 18.3.1-18.3.4.
  • J. J. Morikuni, A. A. Ketterson, M. Tong, J.-W. Seo, K. Nummila, S. M. Kang, I. Adesida, and K. Y. Cheng, “A High Speed Integrated Optoelectronic Photoreceiver,” 1992 Int. Symp. on Circuits and Syst., May 1992, pp. 1368-1371.
  • R. W. Thaik, S. Sapatnekar and S. M. Kang, “iCGEN: A CMOS Integrated Circuit Layout Generator,” Proc. IEEE/ACM Int. Wkshp. on Layout Synthesis, Vol. 2, May 1992, pp. 255-265.
  • S. M. Kang, “Facing Nonlinearities Squarely for MOS VLSI Analysis,” Proc. Moscow A. S. Popov Soc. Int. Seminar on Nonlinear Circuits and Syst., June 1992.
  • A. Dharchoudhury and S. M. Kang, “An Integrated Approach to Realistic Worst-Case Design Optimization of MOS Analog Circuits,” 1992 Des. Automat. Conf., June 1992, pp. 704-709.
  • Y. H. Shih and S. M. Kang, “Analytic Transient Solution of General MOS Circuit Primitives,” IEEE Trans. on Comput.-Aided Des., Vol. 11, no. 6, pp. 719-731, June 1992.
  • C. H. Diaz, C. Duvvury, S. M. Kang, and L. Wagner, “Electrical Overstress (EOS) Power Profiles: A Guideline to Qualify EOS Hardness of Semiconductor Devices,” 1992 EOS/ESD Symp., Vol 4, Dallas, TX, September 1992, pp. 88-94.
  • J. J. Morikuni and S. M. Kang, “An Analysis of Inductive Peaking in Photoreceiver Design,” IEEE J. of Lightwave Technol., Vol. 10, no. 10, pp. 1426-1437, October 1992.
  • C. H. Diaz and S. M. Kang, “New Algorithms for Circuit Simulation of Device Breakdown,” IEEE Trans. on Comput.-Aided Des., Vol. 11, no. 11, pp.1344-1354, November 1992.
  • M. Sriram and S. M. Kang, “Detailed Layer Assignment for MCM Routing,” 1992 Int. Conf. on Comput.-Aided Des., November 1992, pp. 386-389.
  • E. C. Chang and S. M. Kang, “Computationally Efficient Simulation of Lossy Transmission Line by using Numerical Inverse Laplace Transform,” IEEE Trans. on Circuits and Syst., (Special Issue on Simulation, Modeling, and Electrical Design of High-Speed and High-Density Interconnects), Vol. 39, no. 11, pp. 861-868, November 1992.
  • S. Ho and S. M. Kang, “Optoelectronic Memory Array for Switching and Interconnection Networks,” LEOS’92 Conf. Proc., Boston, MA, November 1992, pp. 592-593.
  • R. Thaik, N. Lek, and S. M. Kang, “A New Global Router using Zero-One Linear Integer Programming Techniques for Sea-of-Gates and Custom Logic Arrays,” IEEE Trans. on Comput.-Aided Des., Vol. 11, no. 12, pp. 1479-1494, December 1992.
  • M. S. Unlu, Y. Leblebici, S. M. Kang, and H. Morkoc, “Transient Simulation of Resonant Cavity Enhanced Hetrojunction Photodiodes Under Pulse Illumination,” IEEE Photonics Technol. Lett., Vol. 4, no. 12, pp. 1366-1369, December 1992.
  • Y. Leblebici, M. S. Unlu, and S. M. Kang, “A Novel Method for Mixed Device/Circuit Simulation of Optoelectronic Integrated Circuits,” Proc. IEEE Asia-Pacific Conf. on Circuits and Syst., Sydney, Australia, December 1992, pp. 460-465.


1991

  • H. Y. Chen and S. M. Kang, “iCOACH: A Circuit Optimization Aid for CMOS High-Performance Circuits,” Integration, the VLSI J., Vol. 10, no. 2, pp. 185-212, January 1991.
  • P. Duchene, M. Declercq, and S. M. Kang, “An Integrated Layout System for Sea-of-Gates Module Generation,” Proc. of the European Des. Automat. Conf., February 1991, pp. 237-241.
  • P. Duchene, M. Declercq, and S. M. Kang, “A Simple CMOS Transition Accelerator Circuit,” Electronics Lett., pp. 300-301, February 1991.
  • J. J. Morikuni, D. S. Gao, S. M. Kang, J. A. Priest, and C. L. Balestra, “New Circuit Models of Optical Logic Gates for Computer Simulation,” 1991 Topical Mtg. on Integrated Photonics Research, April 1991, pp. 67-68.
  • J. M. Lee and S. M. Kang, “Testable CMOS Circuits for Logical Testability of Stuck-Open/Stuck-On Faults,” 1991 Midwest Symp. on Circuits and Syst., May 1991.
  • H. Y. Chen and S. M. Kang, “A New Circuit Optimization Technique for High Performance CMOS Circuits,” IEEE Trans. on Comput.-Aided Des., Vol. 10, no. 5, pp. 670-677, May 1991.
  • Y. Leblebici, P. C. Li, S. M. Kang, and I. N. Hajj, “Hierarchical Simulation of Hot-Carrier Induced Damages in VLSI Circuits,” Proc. of Custom Integrated Circuits Conf., May 1991, pp. 29.3.1-29.3.4.
  • C. H. Diaz, S. M. Kang, and Y. Leblebici, “An Accurate Analytical Delay Model for BiCMOS Driver Circuits,” IEEE Trans. Comput.-Aided Des., Vol. 10, no. 5, pp. 577-588, May 1991.
  • Y. H. Shih and S. M. Kang, “A New MOS Circuit Primitive for Fast Timing Simulation,” Proc. of 1991 Int. Symp. on Circuits and Syst., May 1991, pp.2391-2394.
  • Y. H. Shih and S. M. Kang, “ILLIADS: A New Fast MOS Timing Simulator Using Direct Equation-Solving Approach,” Proc. of 28th Des. Automat. Conf., June 1991, pp. 20-25.
  • M. Sriram and S. M. Kang, “A Parallel Min-Cut Technique for Standard Cell Placement Using a Modified Hopfield Neural Network,” Proc. of Int. Conf. on Circuits and Syst., Shenzhen, China, June 1991, pp. 894-897.
  • S. M. Kang, “Computer-Aided Design for VLSI,” Proc. Int. Conf. on Circuits and Syst.,” Shenzhen, China, June 1991, pp. 1-5.
  • D. Zhoz, F. P. Preparata, and S. M. Kang, “Interconnection Delay in Very High-Speed VLSI,” IEEE Trans. on Circuits and Syst., Vol. 38, no 7, pp. 779-790, July 1991.
  • S. M. Kang, “Regular CMOS Structures for VLSI,” Proc. Int. Wkshp. on CMOS VLSI Des., Lausanne, Switzerland, August 1991.
  • S. M. Kang, “High-Speed CMOS Circuits,” Proc. Int. Wkshp. on CMOS VLSI Des., Lausanne, Switzerland, August 1991.
  • T. K. Yu, S. M. Kang, W. Welch, and J. Sacks, “Parametric Yield Optimization of CMOS Analog Circuits by Quadratic Statistical Circuit Performance Models,” Int. J. on Circuit Theory and Appl., Vol. 19, pp. 579-592, November 1991.
  • Y.-H. Shih, Y. Leblebici, and S. M. Kang, “New Simulation Methods for MOS VLSI Timing and Reliability,” Proc. of Int. Conf. on Comput.-Aided Des., pp. 162-165, November 1991


1990

    • S. M. Kang, “Simulation of Optoelectronic Integrated Circuits,” World Congress of Engineers and Scientists, Seoul, Korea, August 1990.
    • W. J. Welch, T. K. Yu, S. M. Kang, and J. Sacks, “Computer Experiments for Quality Control by Parameter Design,” J. of Quality Technol., Vol. 22, no. 1, pp. 15-22, January 1990.
    • D. S. Gao, A. T. Yang, and S. M. Kang, “Accurate Modeling and Simulation of Interconnection Delays and Crosstalks in High-Speed Integrated Circuits,” IEEE Trans. on Circuits and Syst., Vol. 37, no. 1, pp. 1-9, January 1990.
    • P. Gee, M. Y. Wu, S. M. Kang, and I. N. Hajj, “A Metal-Metal Cell Generator for Multi-Level Metal MOS Technology,” Integration, the VLSI J., Vol. 9, no. 1, pp. 25-47, February 1990.
    • Y. Leblebici and S. M. Kang, “A One-Dimensional MOSFET Model for Simulation of Hot-Carrier Induced Device and Circuit Degradation,” Proc. Int. Symp. on Circuits and Syst., May 1990, pp. 109-112.
    • C. H. Diaz, S. M. Kang, and Y. Leblebici, “An Accurate Analytical Delay Model for BiCMOS Driver Circuits,” Proc. Int. Symp. on Circuits and Syst., May 1990, pp. 558-561.
    • M. Sriram and S. M. Kang, “A Modified Hopfield Network for Two-Dimensional Module Placement,” Proc. Int. Symp. on Circuits and Syst., May 1990, pp. 1164-1169.
    • S. M. Kang, “Performance-Driven Layout of CMOS VLSI Circuits,” Proc. Int. Symp. on Circuits and Syst., May 1990, pp. 881-884.
    • S. M. Kang and H. Y. Chen, “A Global Delay Model for Domino CMOS Circuits,” Int. J. on Circuit Theory and Appl., Vol. 18, no. 3, pp.289-306, May 1990.
    • P. Gee, M. Y. Wu, S. M. Kang, and I. N. Hajj, “Automatic Synthesis of Metal-Metal Matrix Layout,” Int. J. of Comput.-Aided VLSI Des., Vol. 2, no. 1, pp. 83-104, 1990.
    • A. T. Yang, S. M. Kang, and G. C. Yang, “An Integrated System for Device Model Design, Circuit Simulation, and Parameter Extraction,” Adv. in Electrical Engr. Electrosoft J. (ed. P. P. Silvester), pp. 31-43, Computational Mechanics Pub., Springer-Verlag, 1990.
    • D. S. Gao, S. M. Kang, R. P. Bryan, and J. J. Coleman, “Modeling of Quantum-Well Lasers for Computer-Aided Analysis of Optoelectronic Integrated Circuits,” IEEE Trans. on Quantum Electronics, Vol. 26, no. 7, pp. 1206-1216, July 1990.
    • S. M. Kang, “Regular CMOS Structures for VLSI,” Proc. Int. Wkshp. on CMOS VLSI Des., Lausanne, Switzerland, September 1990.
    • S. M. Kang, “High-Speed CMOS Circuits,” Proc. Int. Wkshp. on CMOS VLSI Des., Lausanne, Switzerland, September 1990.
    • Y. Leblebici and S. M. Kang, “An Integrated Reliability Simulation Tool for Hot Carrier Resistant VLSI Design,” Proc. 1990 SRC Tech. Conf., October 1990, pp. 102-105.
    • Y. Leblebici and S. M. Kang, “An Integrated Hot-Carrier Degradation Simulator for VLSI Reliability Analysis,” Proc. Int. Conf. on Comput.-Aided Des., November 1990, pp. 400-403.