As the CMOS technology scales down, traditional analog/RF circuit design methodologies are also evolving by exploiting innovative circuit techniques such as low-voltage and sub-threshold circuits, and all digital implementations. Nano-scale CMOS technology offers a potential for small size, high integrity, fast switching speed with finer timing resolution. However, the demand for low power consumption requires that the supply voltage scaling be lowered much faster than the threshold voltage scaling, and thus resulting in the tough voltage headroom problem, especially for the analog/RF circuit designers.
The small headroom causes limited voltage resolutions and thus poor linearity performance. Moreover, along with low output impedance, the deep submicron devices show much poor noise performance since the short channel devices usually generates much higher 1/f noise than the long channel devices, implying that it will be very difficult to achieve wide enough dynamic range offering acceptable signal-to-noise performance. Whereas the downward scaling challenges greatly analog/RF circuit designs, it provides advantages for digital circuits. Current CMOS technology offers cutoff frequencies of up to several hundred GHz, and thus the high speed direct digital implementation even for the GHz range RF signals can be an alternative to get over the limited headroom and linearity problems.

Our group is actively pursuing development of next generation analog/RF circuit techniques exploiting as many digital techniques as possible, eventually for the true Software Defined Radio (SDR) with flexible configurability, which can be easily integrated on a chip together with many types of applications.
Together with high-speed circuit techniques such as GHz range data converters and all-digital frequency synthesizer, our research includes the systematic architectural study to preserve the analog-like high precision and low-noise digital performance, and multi-level high speed bi-directional input/output circuits.

  (a) High resolution data converter
Recently, high-speed and high-accuracy digital-to-analog converters (DACs) have been widely applied to HDTV, video, and modern communication systems. While designing DACs, the important design issues of interest are how to integrate analog circuits together with digital switching circuits on the same chip regarding SOC integrations. In addition, static performance parameters such as offset error, gain error, INL, DNL are also of our interest.
While the static performances of current steering DACs are limited by the random error and systematic error, the dynamic performances are typically limited by three factors: 1) voltage fluctuation in the output nodes due to improper timing; 2) control signal feed-through to the output lines; and 3) imperfect synchronization of the switching signals. In order to achieve high performance, a statistical systematic analysis dealing with the parameter mismatch, transistor gate area, cell switching sequences, and PVT variations are considered.
Along with the systemic analysis and circuit design, we are developing an accurate mathematical model for the transistor size effects and PVT variations to provide an explicit way of performance optimization regarding conversion resolution, linearity, and dynamic performances of SFDR and SNDR.

  (b) Multi-level simultaneous bi-directional high-speed I/O
To accommodate the VLSI trend of rapid increase in circuit size, geometries are being aggressively scaled down. This downscale increases the need to communicate with the external system such as storage, display, or any further data processing. Also, the longer word size and the higher data rate in the chip interface lead to increase in the number of I/O pins in a unit area of a package and the power dissipation as well.

In chip-to-chip communications, the topology of the communications affects the performance of the communication links. Multi-drop is a configuration in which components are all connected to the same set of communication wires. It polls data in sequence over one communication wire that results in a cheaper solution at the expense of response time.
Point-to-point dedicates one communication line between two chips. It is usually preferred for the high speed links that require high reliability even though it comes with large number of I/O. In a point-to-point link, increasing the bandwidth per wire enhances system performance due to limited number of pins. Simultaneous Bidirectional (SBD) signaling was previously introduced to allow simultaneous data transmission in two directions over one wire, doubling the effective bandwidth per pin over a point-to-point unidirectional transmission. The multi-level SBD I/O enhances data rate over SBD I/O at the expense of less voltage distance.
This research is to develop a reliable high speed multi-level simultaneous bi-directional I/O. When an I/O switches data at high speed, it draws a large current abruptly to drive output loads, which causes simultaneous switching noise (SSN) induced by parasitics. A differential scheme is one of the best solutions that make the total sum of AC currents ideally zero. To increase data rate, firstly calibration is considered for the impedance mismatch between the two chips which reduces the voltage margin and for the mismatch between voltage references and incoming signal which degrades Symbol Error Rate (SER). Also, a band-gap reference is used to reduce the effects of supply voltage fluctuation, temperature variation, and chip-to-chip mismatches. Secondly, in an I/O, a large size of current switches limits the bandwidth. A latched differential current switching scheme and pre-emphasis enhance speed in the transmitter. In the receiver end, de-emphasis to a voltage references and a clocked comparator are applied for the higher symbol rate. Simulation based on 0.18um CMOS process show that the proposed design achieves data rate up to 8-Gb/s/pin at the power consumption of 46.8mW with 1.8V power supply. A test chip is developed for experimental verification.