publications

books

patents

papers(2015~now)

papers(2010~2014)

papers(2005~2009)

papers(2000~2004)

papers(95~99)

papers(09~94)


    Patents

 

  1. U.S. Patent 4,396,994, Data shifting and rotating apparatus, August 2, 1983.
  2. U.S. Patent 5,404,041, Source contact placement for efficient ESD/EOS protection in grounded-substrate MOS ICs, April 4, 1995.
  3. U.S. Patent 5,450,267, ESD/EOS protection circuits for integrated circuits, September 12, 1995.
  4. U.S. Patent 5,468,667, Method of placing source contacts for efficient ESD/EOS protection in grounded substrate MOS integrated circuit, November 21, 1995.
  5. U.S. Patent 5,610,774, Optical communications and interconnection networks having optoelectronic switches and direct optical routers, March 11, 1997.
  6. U.S. Patent 5,796,638, Methods, apparatus and computer program products for synthesizing integrated circuits with electrostatic discharge capability and correcting ground rules faults therein, August 18, 1998.
  7. U.S. Patent 5,923,656, Scalable broadband input-queued ATM switch including weight driven cell scheduler, July 13, 1999.
  8. U.S. Patent 6,624,665, CMOS Skewed Static Logic and Method of Synthesis, September 23, 2003.
  9. U.S. Patent 6,759,873, Reverse Biasing Logic Circuit, July 6, 2004.
  10. U.S. Patent 6,784,707, Delay Locked Loop Clock Generator, August 31, 2004.
  11. U.S. Patent 6,784,694, CMOS Sequential Logic Configuration for an Edge Triggered Flip-Flop, August 31, 2004.
  12. U.S. Patent 6,974,903, CMOS Parallel Dynamic Logic and Speed Enhanced Static Logic, September 21, 2004.
  13. U.S. Patent 6,861,911, Self-Regulating Voltage Controlled Oscillator, March 1, 2005.
  14. U.S. Patent 6,900,690, Low Power High Performance Integrated Circuit and Related Methods, May 31, 2005.
  15. U.S. Patent 6,977,528, Event Driven Dynamic Logic for Reducing Power Consumption, December 20, 2005.
  16. U.S. Patent 6,992,915, Self reverse bias low-power high-performance storage circuitry and related methods, January 31, 2006.